rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adm1052 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 precision dual voltage regulator controller features two independent controllers on one chip two 2.525 v outputs shutdown inputs to control each channel 2.5% accuracy over line, load, and temperature low quiescent current low shutdown current works with external n-channel mosfets for low cost hiccup mode fault protection no external voltage or current setting resistors small, 8-lead so package applications desktop computers servers workstations general description the adm1052 is a dual, precision, voltage regulator controller inte nded for power rail generation and active bus termination on personal computer motherboards. it contains a precision 1.2 v bandgap reference and two channels consisting of con- trol amplifiers driving external power devices. each channel has a shutdown input to turn off amplifier output and ?iccup mode protection circuitry for the external power device. the adm1052 operates from a 12 v supply. this gives suffi- cient headroom for the amplifiers to drive external n-channel mosfets, operating as source-followers, as the external series pass devices. this has the advantage that n-channel devices are cheaper than p-channel devices of similar performance, and the circuit is easier to stabilize than one using p-channel devices in a common-source configuration. functional block diagram shdn1 v cc bandgap reference shutdown control hiccup comparator 100 f 2 100 f 3.3v v out1 control amplifier force 1 sense 1 v cc 50 a adm1052 3.3v v out2 force 2 sense 2 shdn2 v cc shutdown control hiccup comparator control amplifier 50 a gnd clock oscillator power-on reset clk/delay generator v cc 100 f 2 100 f
rev. a C2C adm1052?pecifications (v cc = 12 v 6%, v in = 3.3 v, t a = 0 c to 70 c, both channels, unless otherwise noted. see test circuit.) parameter min typ max unit test conditions/comments output voltage channel 1, channel 2 2.525 v shdn1 , shdn2 floating output voltage accuracy ?.5 +2.5 % v in = 3.0 v to 3.6 v, i out = 10 ma to 1 a load regulation ? +5 mv v in = 3.3 v, i out = 10 ma to 1 a 1 line regulation ? +5 mv v in = 3.0 v to 3.6 v, i out = 1 a 1 control amplifier control amplifier open-loop gain 100 db control amplifier slew rate 3 v/ s closed-loop settling time 5 si o = 10 ma to 2 a turn-on time 5 s to 90% of force high output level (c l = 470 pf) sense input impedance 1 50 k ? force output voltage swing, v f (high) 10 v r l = 10 k ? to gnd force output voltage swing, v f (low) 2 v r l = 10 k ? to v cc hiccup mode hiccup mode hold-off time 30 60 90 ms figure 2 hiccup mode threshold 0.8 v out v hiccup comparator glitch immunity 100 s hiccup mode on-time 0.5 1.0 1.5 ms hiccup mode off-time 20 40 60 ms power-on reset threshold 6 9 v shutdown, shdn1 , shdn2 shutdown input low voltage, v il 0.8 v shutdown input high voltage, v ih 2.0 v supply current, normal operation 2.4 4.0 ma shutdown inputs floating supply current, shutdown mode 600 1000 a both channels shut dow n notes 1 guaranteed by design. specifications subject to change without notice.
rev. a adm1052 C3C absolute maximum ratings * (t a = 25 c unless otherwise noted) v cc to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v shdn1 , shdn2 to gnd . . . . . . . . ?.3 v to (v cc + 0.3 v) sense1, sense2 to gnd . . . . . . . . . . . . ?.3 v to +5.5 v force1, force2 . . . . . . . . short-circuit to gnd or v cc continuous power dissipation (t a = 70 c) . . . . . . . 650 mw 8-lead soic . . . . . . . . . . . . (derate 8.3 mw/ c above 70 c) operating temperature range commercial (j version) . . . . . . . . . . . . . . . . . . 0 c to 70 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . 300 c * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. thermal characteristics 8-lead small outline package: ja = 150 c/w ordering guide temperature package package model range description option adm1052jr 0 c to 70 c 8-lead soic so-8 adm1052 100 f 2 100 f 3.3v v out1 force 1 sense 1 3.3v v out2 force 2 sense 2 100 f 2 100 f shdn1 shdn2 leave open or connect to logic signals if shutdown required phd55n03lt mtd3055vl 1 f 12v v cc gnd figure 1. test circuit pin function descriptions pin no. mnemonic function 1 force 2 output of channel 2 control amplifier to gate of external n-channel mosfet. 2 sense 2 in put from source of external mosfet to inverting input of channel 2 control amplifier, via output voltage-setting feed- back resistor network. 3 shdn2 digital input. active-low shutdown control with 50 a internal pull-up. the output of channel 2 control amplifier g oes to ground when shdn2 is taken low. 4 gnd device ground pin. 5 shdn1 digital input. active-low shutdown control with 50 a internal pull-up. the output of channel 1 control amplifier goes to ground when shdn1 is taken low. 6 sense 1 input from source of external mosfet to inverting input of channel 1 control amplifier, via output voltage-setting feedback resistor network. 7 force 1 output of channel 2 control amplifier to gate of external n-channel mosfet. 8v cc 12 v supply. pin configuration top view (not to scale) 8 7 6 5 1 2 3 4 force 2 sense 2 shdn2 gnd v cc force 1 sense 1 shdn1 adm1052 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adm1052 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. a adm1052 C4C typical performance characteristics tek stop: 25.0ms/s 56acqs [] stop: t v 2 v 3 1 t ch1 500mv ch2 20.0mv m 2.00 s ch1 3.53v w b ch3 20.0mv w b w b ch1 t t t tpc 1. line transient response, channel 1 and channel 2 v in ?v 2.536 2.9 v out ?v 2.535 2.534 2.533 2.532 2.531 2.530 2.529 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 tpc 2. line regulation, channel 1 v in v 2.542 2.9 v out v 2.541 2.540 2.539 2.538 2.537 2.536 2.535 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 tpc 3. line regulation, channel 2 current a 2.55 0 output v 2.54 2.53 2.52 2.51 2.50 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 tpc 4. load regulation, channel 1 current a 2.55 0 output v 2.54 2.53 2.52 2.51 2.50 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 tpc 5. load regulation, channel 2 frequency hz 0 10 ripple rejection db 10 20 30 40 50 60 70 100 1k 10k 100k 1m 10m tpc 6. v cc supply ripple rejection
rev. a adm1052 C5C temperature c 2.544 0 output v 2.542 2.540 2.538 2.536 2.534 10 20 30 40 50 60 70 80 90 2.532 2.530 2.528 tpc 7. regulator output voltage vs. temperature tek stop: single seq 50.0ms/s [] stop: t ch1 20.0mv m 1.00 s ch1 45.0mv w b ch1 t 1 t t tpc 8. transient response channel 1, 10 ma to 2 a output load step tek stop: single seq 50.0ms/s [] stop: t ch1 20.0mv m 1.00 s ch1 5.2mv w b ch1 t 1 t t tpc 9. transient response channel 1, 2 a to 10 ma output load step tek stop: single seq 50.0ms/s [] stop: t 1 t ch1 20.0mv m 1.00 s ch1 40mv w b ch1 t t tpc 10. transient response channel 2, 10 ma to 2 a output load step tek stop: single seq 50.0ms/s [] stop: t 1 t ch1 20.0mv m 1.00 s ch1 37.6mv w b ch1 t t tpc 11. transient response channel 2, 2 a to 10 ma output load step tek stop: 10.0ks/s 0acqs [] stop: 1 t ch1 10.0mv m 5.00 s ch1 800mv w b ch1 t t t tpc 12. force output in hiccup mode, channel 1
rev. a adm1052 C6C general description the adm1052 is a dual, precision, voltage regulator controller intended for power rail generation and active bus termination on personal computer m otherboards. it contains a precision 1.2 v bandgap reference and two channels consisting of control amp- lifiers dr iving external power devices. both channels have an output of nominally 2.525 v. each channel has a shutdown input to turn off amplifier output and protection circuitry for the external power device. the adm1052 operates from a 12 v v cc supply. the output is disabled until v cc climbs above the reset threshold (6 v? v). the output from the adm1052 is used to drive external n-channel mosfets, operating as source-followers. this has the advan- tage that n-channel devices are cheaper than p-channel devices of similar performance, and the circuit is easier to stabilize than one using p-channel devices in a common-source configuration. the external power devices are protected by a ?iccup mode circuit that operates if the circuit goes out of regulation due to an output short-circuit. in this case the power device is pulsed on/off with a 1:40 duty cycle to limit the power dissipation until the fault condition is removed. circuit description control amplifiers the reference voltage is amplified and buffered by the control amplifiers and external mosfets, the output voltage of each channel being determined by the feedback resistor network between the sense input and the inverting input of the con- trol amplifier. a power-on reset circuit disables the amplifier output until v cc has risen above the reset threshold (6 v? v). each amplifier output drives the gate of an n-channel power mosfet, whose drain is connected to the unregulated supply input and whose source is the regulated output voltage, which is also fed back to the appropriate sense input of the adm1052. the control amplifiers have high current-drive capability so that they can quickly charge and discharge the gate capacitance of the external mosfet, thus giving good transient response to changes in load or input voltage. shutdown inputs each channel has a separate shutdown input, which may be controlled by a logic signal and allows the output of the regula- tor to be turned on or off. if the shutdown input is held high or not connected, the regulator operates normally. if the shutdown input is held low, the enable input of the control amplifier is turned off and the amplifier output goes low, turning off the regulator. ?iccup mode?fault protection hiccup mode fault protection is a simple method of protecting the external power device without the added cost of external sense resistors or a current sense pin on the adm1052. in the event of a short-circuit condition at the output, the output voltage will fall. when the output voltage of a channel falls 20% below the nominal voltage, this is sensed by the hiccup com- parator and the channel will go into hiccup mode, where the enable signal to the control amplifier is pulsed on and off with a 1:40 duty cycle. to prevent the device inadvertently going into hiccup mode during power-up or during channel enabling, the hiccup mode is held off for approximately 60 ms on both channels. by this time the output voltage should have reached its correct value. in the case of power-up, the hold-off period starts when v cc reaches the power-on reset threshold of 6 v? v. in the case of channel enabling, the hold-off period starts when shdn is taken high. note that the hold-off timeout applies to both channels even if only one channel is disabled/enabled. as the 3.3 v input to the drain of the mosfet is not moni- tored, it should ideally rise at the same or a faster rate than v cc . at the very least it must be available in time for v out to reach its final value before the end of the power-on delay. if the output voltage is still less than 80% of the correct value after the power- on delay, the device will go into hiccup mode until the output voltage exceeds 80% of the correct value during a hiccup mode on-period. of course, if there is a fault condition at the output during power-up, the device will go into hiccup mode after the power-up delay and remain there until the fault condition is removed. the effect of power-on delay is illustrated in figure 2, which shows an adm1052 being powered up with a fault condition. the output current rises to a very high value during the power- on delay, the device goes into hiccup mode, and the output is pulsed on and off at 1:40 duty cycle. when the fault condition is removed, the output voltage recovers to its normal value at the end of the hiccup mode off period. the load current at which the adm1052 will go into hiccup mode is determined by three factors: ?the input voltage to the drain of the mosfet, v in ?the output voltage v out (?0%) ?the on-resistance of the mosfet, r on i hiccup = ( v in ? (0.8 v out ))/ r on it should be emphasized that the hiccup mode is not intended as a precise current limit but as a simple method of protecting the external mosfet against catastrophic fault conditions such as output short circuits.
rev. a adm1052 C7C applications information pcb layout for optimum voltage regulation, the loads should be placed as close as possible to the source of the output mosfets and feedback to the sense inputs should be taken from a point as close to the loads as possible. the pcb tracks from the loads back to the sense inputs should be separate from the output tracks and not carry any load current. similarly, the ground connection to the adm1052 should be made as close as possible to the ground of the loads, and the ground track from the loads to the adm1052 should not carry load current. correct and incorrect layout practice is illustrated in figure 3. 12v supply v ref turn-on threshold por threshold 6v 9v gate drive to external mosfet mosfet gate threshold 3.3v supply to external mosfet drain channel 1 or channel 2 output voltage normal output voltage fault removed output < 0.8 v reg channel 1 or channel 2 output current hiccup mode hold-off time 2 amps device enters hiccup mode fault current 1:40 duty cycle off on figure 2. power-on reset and hiccup mode load 1 load 2 v in 3.3v force 1 force 2 sense 1 sense 2 gnd v cc 12v v out1 v out2 i 1 i 2 load 1 load 2 v in 3.3v force 1 force 2 sense 1 sense 2 gnd v cc 12v v out1 v out2 i 1 + i 2 voltage drop in ground lead voltage drop between output and load i 1 i 2 correct incorrect figure 3. correct and incorrect layout practice
rev. a C8C c02127C0C1/01 (rev. a) printed in u.s.a. adm1052 adm1052 100 f 2 100 f 3.3v v out1 force 1 sense 1 3.3v v out2 force 2 sense 2 100 f 2 100 f shdn1 shdn2 leave open or connect to logic signals if shutdown required 1 f 12v v cc gnd figure 4. typical application circuit supply decoupling the supply to the drain of an external mosfet should be decoupled as close as possible to the drain pin of the device, with a 100 f capacitor to ground. the output from the source of the mosfet should be decoupled as close as possible to the source pin of the device. decoupling capacitors should be chosen to have a low equivalent series resistance (esr). with the mosfets specified and two 100 f capacitors in parallel, the circuit will be stable for load currents up to 2 a. the v cc pin of the adm1052 should be decoupled with a 1 f capacitor to ground, connected as close as possible to the v cc and gnd pins. outline dimensions dimensions shown in inches and (mm). 8-lead small outline package (narrow body, so-8) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 85 4 1 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) in practice, the amount of decoupling required will depend on the application. pc motherboards are notoriously noisy environ- ments, and it may be necessary to employ distributed decoupling to achieve acceptable noise levels on the supply rails. choice of mosfet as previously discussed, the load current at which an output goes into hiccup mode depends on the on-resistance of the external mosfet. if the on-resistance is too low this current may be very high. while the test circuit (figure 1) shows the use of the lower resistance phd55n03lt from philips on channel 1 and the use of the higher resistance mtd3055vl from motorola on channel 2, the mtd3055vl is, in fact, suitable for both channels. similarly, the phb11n06lt from philips is also suitable for both channels. thermal considerations heat generated in the external mosfet must be diss ipated and the junction temperature of the device kept within accept- able limits. the power dissipated in the device is, of course, the drain-source voltage multiplied by the load current. the required thermal resistance to ambient is given by j a = t j ( max ) ? t amb ( max ) /( v ds ( max ) i out ( max ) ) surface-mount mosfets such as those specified must rely on heat c onduction through the device leads and the pcb. one square inch of copper (645 sq. mm) gives a thermal resistance of around 60 c/w for a sot-223 surface-mount package and 80 c/w for a so-8 surface-mount package. for h igher power dissipation than can be accomm odated by a surface-mount package d 2 pak or to-220 devices are recom- mended. these should be mounted on a heatsink with a thermal resistance low enough to maintain the required maximum junc- tion temperature.
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